1. Field of the Invention
This invention relates to matching the coefficient of thermal expansion (CTE) of one semiconductor chip to the CTE of another semiconductor chip and, more particularly to matching the CTE of an ROIC to the CTE of an infrared detector chip.
2. Prior Art
It is known in the art to hybridize different semiconductor chips together to form a hybrid array. One particular example would be hybridizing a readout integrated circuit chip (ROIC) and an infrared detector chip together to form a hybridized infrared detector array or sensor chip assembly (SCA). However, distinct semiconductor chips, such as the ROIC and the infrared detector chip, almost always have substantially different CTE's from one another, which leads to thermal mismatch problems.
One such thermal mismatch problem usually occurs when conducting the hybridization process of the ROIC to the infrared detector chip at elevated temperatures, e.g. 70-200° C. In particular, under elevated hybridization temperatures, if there is a substantial mismatch between the CTE of the ROIC and the infrared detector then a misalignment of the chips will occur. Namely, the indium bump connections between the ROIC and infrared detector chip will become misregistered or misaligned due to thermal mismatch. One result of the above thermal mismatch problems is a lessening of the number of options one has in performing hybridization of these chips.
Another major disadvantage with the prior art hybridized IR detector arrays and processes occurs when the hybridized infrared detector array is thermally cycled between room temperature and the typical 78 K (Kelvin) operating temperature. A problem arises because the ROIC chip (in most cases silicon) has a different CTE than the infrared chip (e.g. HgCdTe/CdZnTe) and a differential contraction will occur. One result is that the indium bump connections between the ROIC and the infrared chip can crack and open leading to circuit failure.
Other problems which typically result from thermal mismatch between the ROIC and the infrared detector chip manifest themselves as physical damage in the hybrid array and degraded performance. The physical damage may manifest itself as either local or global delamination of the hybrid, i.e., actual separation of the indium bumps between the detector and readout circuit, or cracking of the detector array. The performance degradation may manifest itself as a lack of uniformity between arrays, within an array, or as a general reduction in performance specifications.
Some prior art methods have attempted to rectify the above noted drawbacks using approaches discussed below. For example U.S. Pat. No. 5,672,545 to Trautt et al. (“the Trautt patent”) is directed in relevant part to matching the CTE's between an ROIC and an infrared detector chip in order to provide a thermally matched flip-chip assembly. In order to accomplish this, a composite structure is designed to have a CTE which substantially matches the CTE of an infrared detector chip. The composite structure is comprised of the ROIC, a first compensation layer and a second compensation layer. The components of the composite structure are bonded together using epoxy adhesives.
In addition, U.S. Pat. No. 5,308,980 to Barton (“the Barton Patent”) relates in relevant part to a hybrid detector array wherein the ROIC and the infrared detector chip are thermally matched. In particular, the Barton patent describes a hybrid infrared detector array, including a readout circuit chip hybridized to an infrared detector chip. The hybrid detector array further includes a readout circuit substrate having metal constituents which is bonded using epoxy adhesives to the bottom exposed surface of the ROIC to form a composite structure after hybridization has already taken place. The resulting composite structure is designed to have a CTE which is substantially the same as the infrared detector portion.
Further, U.S. Pat. No. 6,417,514 B1 to Eneim et al. relates in relevant part to a sensor/support system which includes a sensor assembly having a radiation detector, a readout circuit, and an interconnect joining the radiation detector to the readout circuit. The system further includes a support structure having a platform with a first side to which the sensor assembly is affixed and a second side oppositely disposed from the first side. A shim is affixed to the second side of the platform. The shim is designed to reduce the strain in the interconnect when the temperature of the sensor/support system is changed, as compared with the strain in the interconnect in the absence of the stabilization structure.
While some of the prior art noted above has addressed the issue of thermal mismatch between a readout circuit and an infrared detector chip, there is still a need in the art for an apparatus and method wherein the CTE of the ROIC is substantially matched to the infrared detector prior to hybridization. There is also a need in the art for a process of preparing a hybridized infrared detector array without the use of any adhesives, such as epoxy adhesives. The present invention fulfills these needs, and further provides related advantages.